LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


ENTITY delay_unit IS
PORT
	(
		clk		           : IN STD_LOGIC;
		
		write_request       : out std_logic;
    write_request_addr  : out std_logic_vector(17 downto 0);
    write_request_data  : out std_logic_vector(15 downto 0);
    write_request_ack   : in std_logic;
    
    op1                 : IN unsigned(31 downto 0);
		op2                 : IN unsigned(31 downto 0);
		inst                : in unsigned(31 downto 0);
    
    finished : out std_logic
	);
END delay_unit;



ARCHITECTURE bhv OF delay_unit IS

 signal inst_buffer : unsigned (31 downto 0) := (others => '0');

 signal addr_buffer : std_logic_vector(17 downto 0) := (others => '0');
 signal data_buffer : std_logic_vector(15 downto 0) := (others => '0');
 signal wait_for_ack : std_logic := '0';

BEGIN
  

	process (clk)
	begin
	 if rising_edge(clk) then
	   
	   inst_buffer <= inst;
	   
	   if inst_buffer(31 downto 30)="11" then
	     wait_for_ack<='1';
	     addr_buffer <= std_logic_vector(op1(17 downto 0));
	     data_buffer <= std_logic_vector(op2(15 downto 0));
	   end if;
	   
	   if write_request_ack='1' then
	     wait_for_ack<='0';  
	   end if;
	    
	 end if;
	end process;
	
	finished <= write_request_ack;
	
	write_request <= wait_for_ack;
	write_request_addr <= addr_buffer;
	write_request_data <= data_buffer;
 
END bhv;


